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| geometry process details principal device types cmkt5089m10 cmst5089 2n4104 gross die per 5 inch wafer 102,852 process CP388X small signal transistor npn - low noise amplifier transistor chip process epitaxial planar die size 13 x 13 mils die thickness 5.9 mils base bonding pad area 3.9 x 3.9 mils emitter bonding pad area 5.4 x 5.4 mils top side metalization al-si - 17,000? back side metalization au - 12,000? backside collector r0 www.centralsemi.com r2 (29-april 2010) http://
process CP388X typical electrical characteristics www.centralsemi.com r2 (29-april 2010) http:// |
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